Modeling and performance analysis of RISC-V pipeline architectures using discrete-event simulation in a queuing simulator

Background

The efficiency of modern microprocessors relies heavily on the principle of pipelining, that is, the parallel processing of different instruction phases. While classic RISC architecture is often based on a five-stage pipeline, alternative approaches such as three-stage pipelines also exist. To understand the effects of these design decisions on throughput and latency, abstract modeling based on queueing theory is a valuable tool.

Objective of the thesis

The goal of this thesis is to model various pipeline implementations of a RISC-V processor using the queuing simulator tool “Warteschlangensimulator”. The aim is to quantify and analyze the theoretical differences between a classical five-stage architecture and a three-stage design through simulation.

Work steps and focus areas

As part of this project, the student is expected to address the following points:

  1. Theoretical foundations:
    • Familiarization with the RISC-V architecture.
    • Analysis of the concept of pipelining and specific challenges (hazards, stalls, forwarding).
    • Comparison of the theoretical concepts of a classic five-stage pipeline (fetch, decode, execute, memory, write-back) with a three-stage variant.
  2. Modeling in the queueing simulator:
    • Abstraction of the processor stages as service stations within a queueing system.
    • Creation of a model for the five-stage RISC-V pipeline.
    • Development of a corresponding model for the three-stage pipeline.
  3. Simulation and experiments:
    • Definition of load profiles (instruction mix ratios) to simulate different program scenarios.
    • Conducting simulation runs to determine key metrics such as utilization, turnaround times, and throughput (IPC—Instructions Per Cycle).
  4. Analysis and evaluation:
    • Comparison of the simulation results for both architectures.
    • Discussion of the advantages and disadvantages of the three-stage pipeline versus the five-stage pipeline in terms of performance and complexity.

Supervision

Supervision of this thesis is provided in cooperation with Alexander Herzog from the Center for Simulation Science (SWZ), particularly with regard to the subject-specific use and configuration of the queueing simulator.

References

  • D. A. Patterson and J. L. Hennessy, *Computer organization and design RISC-V edition: the hardware software interface*, 2nd edition. Cambridge, MA: Morgan Kaufmann, 2021. ISBN: 978-0-12-820331-6
  • M. Schoeberl, “Wildcat: educational RISC-V microprocessors,” in Architecture of Computing Systems. Springer Nature Switzerland, Oct. 2025, pp. 189–202. doi: 10.1007/978-3-032-03281-2_13. Available: www.jopdesign.com/doc/wildcat-arcs.pdf
  • A. Herzog, Simulation with the Queueing Simulator: Mathematical Modeling and Simulation of Production and Logistics Processes. Springer Fachmedien, 2021. doi: 10.1007/978-3-658-34668-3. ISBN: 978-3-658-34667-6A.
  • Herzog and S. G, A-Herzog/Queueing Simulator: Queueing Simulator - Version 5.9. (Oct. 13, 2025). Zenodo. doi: 10.5281/zenodo.17337674. Available: zenodo.org/records/17337674
  • “Warteschlangensimulation” Available: www.simzentrum.de/forschungsprojekte/warteschlangensimulation